1. Technical Field
This invention relates to semiconductor memory systems and techniques for increasing effective production yield by the implementation of redundant memory cells, and particularly to the implementation of wordline redundancy.
2. Prior Art
The application of memory cell redundancy to enhance the yield of semiconductor memory arrays during the early stages of mass production is extensively practiced throughout the semiconductor industry. The classic problem encountered when implementing wordline redundancy is that of containing the address detection and word drive steering functions without increasing the time interval between word address generation and wordline drive. In high performance DRAM architecture there are normally four clock phases between the application of word address signals to the memory and the actual wordline drive phase. The first phase begins with the application of the word addresses to an input buffer circuit. The second is that of the address drive signal. The third phase drives both true and complement word address signals to the word decoders distributed across the memory chip. The fourth is that of the actual wordline drive phase which can be applied only after all of the unselected word decoders have responded to the true/complement address signals. The critical time during which the determination of whether to activate normal or redundant word lines lies between phases three and four, since the selection cannot be made until after the true/complement address signals have been evaluated. Except in those few instances described below, prior art techniques for implementing wordline redundancy require that the timing between these critical phases be increased considerably. Other techniques for obtaining wordline redundancy, although not presenting the same problem, have problems of their own.
Previous designs of wordline redundancy have been proposed at the expense of:
Increased chip area and circuit complexity caused by the use of independent columns of sense amplifiers and data line steering circuits operating in parallel with the normal array circuitry, see for example the article by B. F. Fitzgerald and E. P. Thoma, "Circuit Implementation of Fusible Redundant Addresses on RAMs for Productivity Enhancement", IBM Journal of Research and Development, Vol. 24, No. 3, pp. 291-295, May 1980. Here wordline redundancy is implemented without an access time penalty by adding separate sense amplifier columns for the redundant wordlines. No access penalty is incurred because the redundant wordline and the defective wordline operate in parallel, and the selection of the redundant, versus the normal sense amplifiers, occurs during the sensing operation. This approach is disadvantageous in that chip size is significantly increased due to the need for additional latches for each bitline along the redundant wordline.
U.S. Pat. No. 4,365,319, issued to Takemae on Dec. 21, 1982, implements redundancy by utilizing two kinds of decoders and drivers, i.e., a PROM decoder for determining whether an incoming address is a defective address, a redundancy driver for driving a redundancy array, and row address decoders and drivers for driving a main memory cell matrix. A first embodiment of the Takemae teachings (FIG. 1) is disadvantageous in that the switch 7 results in an access time penalty, and results in a semiconductor space penalty because the switch must be large to handle high currents. In a second embodiment (FIGS. 2-4), multiple AND gates D.sub.-0 -D.sub.63 replace the large switch 7 (FIG. 1); however, this is not much of an improvement because the memory device still suffers from both an access time (i.e., an AND-gate) penalty, and also a semiconductor space penalty as the collective area of the AND gates D.sub.0 -D.sub.63 is still large. A third embodiment (FIGS. 5-10) suffers an access time penalty due to AND-gate delays introduced by the incorporation of AND gates D.sub.91 -D.sub.94 (FIG. 6) and AND gates D.sub.0 -D.sub.3 (FIG. 8A) to control the activation of the decoders and drivers 9 and 10, respectively.
The Intel 2164A 64K DRAM represents a memory device where access time is the same whether it is the normal wordlines or the redundancy wordlines which are being used; however, this product is always affected by an access time penalty, whether repaired with wordline redundancy or not, because chip timing is set up to allow for redundancy repairs. More specifically, chip performance is slowed due to the need to deselect a faulty wordline's word decoder after the redundant word decoders sense a match with an incoming address. Once the match is sensed, a deselect generator is fired or triggered to deselect the entire row of normal word decoders. After the faulty wordline word decoder is deselected, then the wordline drive is enabled. Further discussions concerning the 2164A can be seen in the Intel Application Description AP-131, pp. 14-16, and "An Analysis of the i2164A," Mosaid Incorporated, p. 5, 41-52, April 1982.
The 64K DRAM (described by R. T. Smith, J. D. Chlipala, J. F. M. Bindels, R. G. Nelson, F. H. Fischer and T. F. Mantz, in "Laser Programmable Redundancy and Yield Improvement in a 64K DRAM," IEEE Journal of Solid-State Circuits, Vol, SC-16, No. 5, pp. 506-514, October 1981), and the 256K DRAM (described by C. A. Benevit, J. M. Cassard, K. J. Dimmler, A. C. Dumbri, M. G. Mound, F. J. Procyk, W. R. Rosenzweig and A. W. Yanof, in "A 256K Dynamic Random Access Memory," IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 5, pp. 857-861, October 1982), implement wordline redundancy without an access time impact by using laser-fused redundancy on the wordline pitch. No access time penalty is incurred because the defective wordline is permanently disconnected by an exploding programmable link provided in each of the wordline drive circuits. This method of redundancy is disadvantageous because the tighter design rules of present and future high density memory products are causing a shrinkage in the wordline pitch. The result is a requirement for a laser spot size and laser beam position accuracy beyond what is available from laser programming systems today. Thus, laser-fused redundancy is disadvantageous in that the current level of laser technology requires an off wordline pitch method or an increase in memory chip size due to the need for an increased wordline pitch.
Our copending U.S. application serial number 176,473 filed Apr. 1, 1988, now U.S. Pat. No. 4,885,720 teaches a circuit and method of providing wordline redundancy without impact on access time at the expense of providing separate wordline driver circuits for the normal and redundant array cells. This design also requires excess power and complex circuitry to implement effectively.
Additional designs have also been described which include design trade-offs such as:
increased access time caused by driving both true and complement addresses signals high after redundant address compare circuitry has completed its function, see U.S. Pat. No. 4,389,715 to Eaton et al, issued Jun. 21, 1983;
reduced array signal margin due to wordline signal glitches caused by partial selection and then deselection of normal wordline drive phase, see U.S. Pat. No. 4,392,211 to Nakano et al, issued Jul. 5, 1983; and
complex timing considerations caused by introducing an extra timing phase between word address drive time and wordline decode drive, see U.S. Pat. No. 4,723,277 to Murotani, issued Feb. 2, 1988.
While the above approaches represent important advances in semiconductor manufacturing technology, there still exists a need for a memory design approach which is capable of providing wordline redundancy without the disadvantages cited above, i.e., without any access time penalty, and without any significant impact on chip size and power requirements.